High voltage lateral double-diffused metal oxide semiconductor field effect transistor (ldmosfet) having a deep fully depleted drain drift region

ABSTRACT

Disclosed are semiconductor structures. Each semiconductor structure can comprise a substrate and at least one laterally double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) on the substrate. Each LDMOSFET can have a fully-depleted deep drain drift region (i.e., a fully depleted deep ballast resistor region) for providing a relatively high blocking voltage. Different configurations for the drain drift regions are disclosed and these different configurations can also vary as a function of the conductivity type of the LDMOSFET. Additionally, each semiconductor structure can comprise an isolation band positioned below the LDMOSFET and an isolation well positioned laterally around the LDMOSFET and extending vertically to the isolation band such that the LDMOSFET is electrically isolated from both a lower portion of the substrate and any adjacent devices on the substrate.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Divisional of U.S. application Ser. No. 14/672,865filed Mar. 30, 2015, that is a Divisional of U.S. application Ser. No.13/959,777 filed Aug. 6, 2013, issued as U.S. Pat. No. 9,059,278 on Jun.16, 2015, the complete disclosures of which, in their entirety, areherein incorporated by reference.

BACKGROUND

The semiconductor structures disclosed herein relate to lateraldouble-diffused metal oxide semiconductor field effect transistors(LDMOSFETS) and, more particularly, LDMOSFETS having a relatively deep,fully-depleted, drain drift region for providing ballasting resistance.

Typically, an LDMOSFET, like a conventional MOSFET, comprises a channelregion positioned laterally between a source region and a drain region.However, unlike the conventional MOSFET, the LDMOSFET is asymmetrical.Specifically, the drain region of the LDMOSFET is separated from thechannel region by a relatively low-doped drain drift region, whichprovides ballasting resistance so that the LDMOSFET has a relativelyhigh blocking voltage (i.e., a high maximum voltage that can be appliedto the transistor). However, as operating voltages and device densitiesincrease, LDMOSFETs with even higher blocking voltages and bettertransistor-to-substrate and/or transistor-to-transistor isolation areneeded to prevent device failures.

SUMMARY

In view of the foregoing, disclosed herein are semiconductor structures.Each semiconductor structure can comprise a substrate and a laterallydouble-diffused metal oxide semiconductor field effect transistor(LDMOSFET) on the substrate. Each LDMOSFET can have a fully depleteddeep drain drift region (i.e., a fully depleted deep ballast resistorregion) for providing a relatively high blocking voltage. Differentconfigurations for the drain drift regions are disclosed and thesedifferent configurations can also vary as a function of the conductivitytype of the LDMOSFET. Additionally, each semiconductor structure cancomprise an isolation band positioned below the LDMOSFET and anisolation well positioned laterally around the LDMOSFET and extendingvertically to the isolation band such that the LDMOSFET is electricallyisolated from both a lower portion of the substrate and any adjacentdevices on the substrate.

More particularly, disclosed herein is a semiconductor structurecomprising a semiconductor substrate. This semiconductor substrate canhave a first type conductivity at a relatively low conductivity level(e.g., a P− substrate).

The semiconductor structure can further comprise a transistor (e.g., aP-type lateral double-diffused metal oxide semiconductor field effecttransistor (PLDMOSFET)) on the substrate. Specifically, the transistorcan comprise a plurality of intra-transistor wells within the substrate.These intra-transistor wells can comprise a first intra-transistor wellhaving the first type conductivity (e.g., a P-well); a secondintra-transistor well positioned laterally adjacent to the firstintra-transistor well and having a second type conductivity (e.g., anN-well); a third intra-transistor well positioned laterally adjacent tothe second intra-transistor well and having the first type conductivity(e.g., another P-well); and a fourth intra-transistor well positionedlaterally adjacent to the third intra-transistor well and having thesecond type conductivity (e.g., another N-well).

The transistor can further comprise, within the substrate at the topsurface, a drain region, a source region, one or more contact regionsand a trench isolation structure that electrically isolates theseregions. Specifically, the transistor can comprise a drain region withinthe first intra-transistor well at the top surface of the substrate anda source region within the fourth intra-transistor well at the topsurface of the substrate. The drain region and the source region caneach have the first type conductivity at a relatively high conductivitylevel (e.g., a P+drain region and a P+ source region). The transistorcan comprise a contact region within the fourth intra-transistor well atthe top surface of the substrate. This contact region can have thesecond type conductivity at a relatively high conductivity level (e.g.,an N+ contact region). Optionally, this transistor can further compriseanother contact region, having the second type conductivity at arelatively high conductivity level (e.g., another N+ contact region),within the second intra-transistor well at the top surface of thesubstrate. As mentioned above, the drain region, source region and anycontact regions can be electrically isolated by a trench isolationstructure.

The transistor can also comprise an intra-transistor band in thesubstrate below and in contact with the first intra-transistor well, thesecond intra-transistor well, the third intra-transistor well and thefourth intra-transistor well. This intra-transistor band can have thefirst type conductivity (e.g., a P-band).

The semiconductor structure can further comprise, within the substrate,a first isolation well, a second isolation well and an isolation band.The first isolation well can be positioned laterally around (i.e., canborder) the transistor and can have the second type conductivity (e.g.,an N-type isolation well). The second isolation well can be positionedlaterally between the fourth intra-transistor well and the firstisolation well, can have the first type conductivity (e.g., a P-typeisolation well) and can extend vertically to the intra-transistor band.The second isolation band can be below and in contact with the firstisolation well and the intra-transistor band and can have the secondtype conductivity (e.g., an N-type isolation band) such that thetransistor is electrically isolated from both a lower portion of thesubstrate and adjacent devices on the substrate.

In such a semiconductor structure, the transistor will have a fullydepleted deep drain drift region located within the intra-transistorband between the second intra-transistor well and the isolation band.This fully depleted drain drift region will ensure that the transistorhas a relatively high blocking voltage.

Also disclosed herein is another semiconductor structure comprising asemiconductor substrate. This semiconductor substrate can have a firsttype conductivity at a relatively low conductivity level (e.g., a P−substrate).

The semiconductor structure can further comprise a transistor (e.g., aP-type lateral double-diffused metal oxide semiconductor field effecttransistor (PLDMOSFET)) on the substrate. Specifically, the transistorcan comprise a plurality of intra-transistor wells within the substrate.These intra-transistor wells can comprise a first intra-transistor wellhaving the first type conductivity (e.g., a P-well) and a secondintra-transistor well positioned laterally adjacent to the firstintra-transistor well and having a second type conductivity (e.g., anN-well).

This transistor can further comprise, within the substrate at the topsurface, a drain region, a source region, one or more contact regionsand a trench isolation region that electrically isolates these regions.Specifically, the transistor can comprise a drain region within thefirst intra-transistor well at the top surface of the substrate and asource region within the second intra-transistor well at the top surfaceof the substrate. The drain region and the source region can each havethe first type conductivity at a relatively high conductivity level(e.g., a P+ drain region and a P+ source region). The transistor cancomprise a contact region within the second intra-transistor well at thetop surface of the substrate. This contact region can have the secondtype conductivity at a relatively high conductivity level (e.g., an N+contact region). This transistor can also comprise another contactregion, having the second type conductivity at a relatively highconductivity level (e.g., another N+ contact region), within the firstintra-transistor well at the top surface of the substrate between thedrain region and the second intra-transistor well. As mentioned above,the drain region, source region and any contact regions can beelectrically isolated by a trench isolation structure.

The transistor can also comprise an intra-transistor band. Thisintra-transistor band can be positioned in the substrate below and incontact with the first intra-transistor well and the secondintra-transistor well. This intra-transistor band can have the firsttype conductivity (e.g., a P-band).

The semiconductor structure can further comprise a first isolation well,a second isolation well, and an isolation band. The first isolation wellcan be positioned laterally around (i.e., can border) the transistor andcan have the second type conductivity (e.g., an N-type isolation well).The second isolation well can be positioned laterally between the secondintra-transistor well and the first isolation well, can have the firsttype conductivity (e.g., a P-type isolation well) and can extendvertically to the intra-transistor band. The isolation band can be belowand in contact with the first isolation well and the intra-transistorband and can have the second type conductivity (e.g., an N-typeisolation band) such that the transistor is electrically isolated fromboth a lower portion of the substrate and adjacent devices on thesubstrate.

In such a semiconductor structure, the transistor will have a fullydepleted deep drain drift region located within the firstintra-transistor well and the intra-transistor band between the contactregion and the isolation band. This fully depleted drain drift regionwill ensure that the transistor has a relatively high blocking voltage.

Also disclosed herein is yet another semiconductor structure comprisinga semiconductor substrate. This semiconductor substrate can have with afirst type conductivity at a relatively low conductivity level (e.g., aP− substrate).

The semiconductor structure can further comprise a transistor (e.g., anN-type lateral double-diffused metal oxide semiconductor field effecttransistor (NLDMOSFET)) on the substrate. Specifically, the transistorcan comprise a plurality of intra-transistor wells within the substrate.These intra-transistor wells can comprise a first intra-transistor wellin the substrate and having a second type conductivity (e.g., anN-well); a second intra-transistor well in the substrate within thefirst intra-transistor well and having the first type conductivity(e.g., a P-well); and a third intra-transistor well positioned laterallyadjacent to the first intra-transistor well and having the first typeconductivity (e.g., another P-well). In this case, the firstintra-transistor well can extend a first depth into the substrate fromthe top surface, the second intra-transistor well can extend a seconddepth into the substrate from the top surface and the first depth can bedeeper than the second depth (i.e., the second intra-transistor well canbe a more shallow well than the first intra-transistor well).

This transistor can further comprise, within the substrate at the topsurface, a drain region, a source region, one or more contact regions,and a trench isolation structure that electrically isolates theseregions. Specifically, the transistor can comprise a drain region withinthe first intra-transistor well at the top surface of the substrate anda source region within the third intra-transistor well at the topsurface of the substrate. The drain region and the source region caneach have the second type conductivity at a relatively high conductivitylevel (e.g., a N+ drain region and a N+ source region). The transistorcan also comprise a contact region within the third intra-transistorwell. This contact region can have the first type conductivity at arelatively high conductivity level (e.g., a P+ contact region).Optionally, this transistor can further comprise another contact region,having the first type conductivity at a relatively high conductivitylevel (e.g., another P+ contact region), within the secondintra-transistor well at the top surface of the substrate. As mentionedabove, the drain region, source region and any contact regions can beelectrically isolated by a trench isolation structure.

The semiconductor structure can further comprise, within the substrate,a first isolation band, a first isolation well, a second isolation welland a second isolation band. Specifically, the first isolation band canbe positioned below and in contact with the first intra-transistor well.This first isolation band can have the first type conductivity (e.g., aP-type isolation band). The first isolation well can have the secondtype conductivity (e.g., an N-type isolation well) and can be positionedlaterally around (i.e., can border) the transistor. The second isolationwell can have the first type conductivity (e.g., a P-type isolationwell) and can be positioned laterally between the first isolation welland the first intra-transistor well of the transistor and can extendvertically to the first isolation band. The second isolation band can bebelow the first isolation well, the first isolation band and the secondintra-transistor well of the transistor and can have the second typeconductivity (e.g., an N-type isolation band) such that the transistoris electrically isolated from a lower portion of the substrate andadjacent devices on the substrate.

In such a semiconductor structure, the transistor will have a fullydepleted deep drain drift region located within the firstintra-transistor well between the second intra-transistor well and thefirst isolation band. This fully depleted drain drift region will ensurethat the transistor has a relatively high blocking voltage.

Also disclosed herein is yet another semiconductor structure comprisinga semiconductor substrate with a first type conductivity at a relativelylow conductivity level (e.g., a P− substrate).

The semiconductor structure can further comprise a transistor (e.g., anN-type lateral double-diffused metal oxide semiconductor field effecttransistor (NLDMOSFET)) on the substrate. Specifically, the transistorcan comprise a plurality of intra-transistor wells within the substrate.These intra-transistor wells can comprise a first intra-transistor wellin the substrate and having a second type conductivity (e.g., an N-well)and a second intra-transistor well in the positioned laterally adjacentto the first intra-transistor well and having the first typeconductivity (e.g., a P-well).

This transistor can further comprise, within the substrate at the topsurface, a drain region, a source region, one or more contact regionsand a trench isolation region electrically isolating those regions.Specifically, the transistor can further comprise a drain region withinthe first intra-transistor well at the top surface of the substrate anda source region within the second intra-transistor well at the topsurface of the substrate. The drain region and the source region caneach have the second type conductivity at a relatively high conductivitylevel (e.g., a N+ drain region and a N+ source region). The transistorcan also comprise a contact region within the second intra-transistorwell. This contact region can have the first type conductivity at arelatively high conductivity level (e.g., a P+ contact region). Thistransistor can also comprise another contact region, having the firsttype conductivity at a relatively high conductivity level (e.g., anotherP+ contact region), within the first intra-transistor well at the topsurface of the substrate. As mentioned above, the drain region, sourceregion and any contact regions can be electrically isolated by a trenchisolation structure.

The semiconductor structure can further comprise, within the substrate,a first isolation band, a first isolation well, a second isolation welland a second isolation band. Specifically, the first isolation band canbe positioned below and in contact with the first intra-transistor well.This first isolation band can have the first type conductivity (e.g., aP-band). The first isolation well can have the second type conductivity(e.g., an N-type isolation well) and can be positioned laterally around(i.e., can border) the transistor. The second isolation well can havethe first type conductivity (e.g., a P-type isolation well) and can bepositioned laterally between the first isolation well and the firstintra-transistor well of the transistor and can extend vertically to thefirst isolation band. The second isolation band can be below the firstisolation well, the first isolation band and the second intra-transistorwell of the transistor and can have the second type conductivity (e.g.,an N-band) such that the transistor is electrically isolated from alower portion of the substrate and adjacent devices on the substrate.

In such a semiconductor structure, the transistor will have a fullydepleted deep drain drift region located within the firstintra-transistor well between the contact region and the first isolationband. This fully depleted drain drift region will ensure that thetransistor has a relatively high blocking voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments herein will be better understood from the followingdetailed description with reference to the drawings, which are notnecessarily drawn to scale and in which:

FIG. 1 is a vertical cross-section diagram illustrating a P-type lateraldouble-diffused metal oxide semiconductor field effect transistor;

FIG. 2 is a vertical cross-section diagram illustrating another P-typelateral double-diffused metal oxide semiconductor field effecttransistor;

FIG. 3 is a horizontal cross-section diagram further illustrating theP-type lateral double-diffused metal oxide semiconductor field effecttransistor of FIG. 1 or FIG. 2;

FIG. 4 is a vertical cross-section diagram illustrating yet anotherP-type lateral double-diffused metal oxide semiconductor field effecttransistor;

FIG. 5 is a horizontal cross-section diagram further illustrating theP-type lateral double-diffused metal oxide semiconductor field effecttransistor of FIG. 4;

FIG. 6 is a vertical cross-section diagram illustrating an N-typelateral double-diffused metal oxide semiconductor field effecttransistor;

FIG. 7 is a vertical cross-section diagram illustrating another N-typelateral double-diffused metal oxide semiconductor field effecttransistor;

FIG. 8 is a horizontal cross-section diagram further illustrating theN-type lateral double-diffused metal oxide semiconductor field effecttransistor of FIG. 6 or FIG. 7;

FIG. 9 is a vertical cross-section diagram illustrating yet anotherN-type lateral double-diffused metal oxide semiconductor field effecttransistor;

FIG. 10 is a horizontal cross-section diagram further illustrating theN-type lateral double-diffused metal oxide semiconductor field effecttransistor of FIG. 9;

FIG. 11 is a vertical cross-section diagram illustrating an exemplaryinverter comprising the transistors of FIGS. 1 and 6;

FIG. 12 is a vertical cross-section diagram illustrating anotherexemplary inverter comprising the transistors of FIGS. 2 and 7;

FIG. 13 is a vertical cross-section diagram illustrating yet anotherexemplary inverter comprising the transistors of FIGS. 4 and 9; and

FIG. 14 is a vertical cross-section diagram illustrating two of thetransistors of FIG. 1 stacked.

DETAILED DESCRIPTION

As mentioned above, typically, a lateral double-diffused metal oxidesemiconductor field effect transistor (LDMOSFET), like a conventionalMOSFET transistor, comprises a channel region positioned laterallybetween a source region and a drain region. However, unlike theconventional MOSFET, the LDMOSFET is asymmetrical. Specifically, thedrain region of the LDMOSFET is separated from the channel region by arelatively low-doped drain drift region, which provides ballastingresistance so that the LDMOSFET has a relatively high blocking voltage(i.e., a high maximum voltage that can be applied to the transistor).However, as operating voltages and device densities increase, LDMOSFETswith even higher blocking voltages and better transistor-to-substrateand/or transistor-to-transistor isolation are needed to prevent devicefailures.

In view of the foregoing, disclosed herein are semiconductor structures.Each semiconductor structure can comprise a substrate and a laterallydouble-diffused metal oxide semiconductor field effect transistor(LDMOSFET) on the substrate. Each LDMOSFET can have a fully depleteddeep drain drift region (i.e., a fully depleted deep ballast resistorregion) for providing a relatively high blocking voltage. Differentconfigurations for the drain drift regions are disclosed and thesedifferent configurations can also vary as a function of the conductivitytype of the LDMOSFET. Additionally, each semiconductor structure cancomprise an isolation band positioned below the LDMOSFET and anisolation well positioned laterally around the LDMOSFET and extendingvertically to the isolation band such that the LDMOSFET is electricallyisolated from both a lower portion of the substrate and any adjacentdevices on the substrate.

It should be noted that in the semiconductor structures described below,for illustration purposes, the first type conductivity is referred to asbeing P-type conductivity and the second type conductivity is referredto as being N-type conductivity. However, alternatively, the reverse canbe true. That is, the first type conductivity can comprise N-typeconductivity and the second type conductivity can comprise P-typeconductivity. Those skilled in the art will recognize that differentdopants can be used to achieve the different type conductivities andthat the dopants may vary depending upon the different semiconductormaterials used. For example, a silicon-based semiconductor materialhaving N-type conductivity is typically doped with an N-type dopant(e.g., a Group V dopant, such as arsenic (As), phosphorous (P) orantimony (Sb)), whereas a silicon-based semiconductor material havingP-type conductivity is typically doped with a P-type dopant (e.g., aGroup III dopant, such as boron (B) or indium (In)). Alternatively, agallium nitride (GaN)-based semiconductor material having P-typeconductivity is typically doped with magnesium (Mg), whereas a galliumnitride (GaN)-based semiconductor material having a N-type conductivityis typically doped with silicon (Si). Those skilled in the art will alsorecognize that different conductivity levels will depend upon therelative concentration levels of the dopants.

Referring to FIGS. 1 and 2 disclosed herein is a semiconductor structure100 comprising a bulk semiconductor substrate 101. For example, thesemiconductor substrate 101 can comprise a bulk silicon substrate or anyother bulk semiconductor substrate. The semiconductor substrate 101 canhave a first type conductivity (e.g., P-type conductivity) at arelatively low conductivity level. For example, the semiconductorsubstrate 101 can comprise a P− substrate.

The semiconductor structure 100 can further comprise a transistor 1A, asin FIG. 1, or 1B, as in FIG. 2, on the semiconductor substrate 101 and,particularly, a P-type lateral double-diffused metal oxide semiconductorfield effect transistor (PLDMOSFET) on the substrate 101.

Specifically, the transistor 1A, 1B can comprise a plurality ofintra-transistor wells 104-107 within the substrate 101. For purposes ofthis disclosure, an “intra-transistor well” refers to a well (i.e., adopant implant region), which is an active component of the transistor.These intra-transistor wells can comprise, for example, a firstintra-transistor well 104 having the first type conductivity (e.g., aP-well); a second intra-transistor well 105 positioned laterallyadjacent to the first intra-transistor well 104 and having a second typeconductivity (e.g., an N-well); a third intra-transistor well 106positioned laterally adjacent to the second intra-transistor well 105and having the first type conductivity (e.g., another P-well); and afourth intra-transistor well 107 positioned laterally adjacent to thethird intra-transistor well 106 and having the second type conductivity(e.g., another N-well). Each of these intra-transistor wells 104-107 canbe positioned at the top surface 120 of the semiconductor substrate 101and can extend vertically into the semiconductor substrate 101 somepredetermined depth (e.g., a same predetermined depth 121).

It should be noted that the third intra-transistor well 106 can bephysically separated from the fourth intra-transistor well 107 by aspace 141, as shown. In this case, the space 141 between the thirdintra-transistor well 106 and fourth intra-transistor well 107 will havethe same doping type and conductivity level as the lower portion 191 ofthe substrate 101 (e.g., P−). Alternatively, the third intra-transistorwell 106 can be immediately adjacent to (i.e., can abut) the fourthintra-transistor well 107 (not shown).

The transistor 1A, 1B can further comprise a gate structure 130 on thetop surface 120 of the substrate 101. A first side 131 of the gatestructure 130 can extend laterally over the third intra-transistor well106. A second side 132 of the gate structure 130 can extend laterallyover the fourth intra-transistor well 107 and can define the channelregion 140 of the transistor 1A, 1B. The gate structure 130 can comprisea gate dielectric layer (e.g., a gate oxide layer, a high-k gatedielectric layer or other suitable gate dielectric layer) and a gateconductor layer (e.g., a polysilicon gate conductor layer, a metal gateconductor layer, a dual work function gate conductor layer or othersuitable gate conductor layer) on the gate dielectric layer.

The transistor 1A, 1B can further comprise, at the top surface 120 ofthe substrate 101 on either side of the gate structure 130, a drainregion 111, a source region 112, various contact regions (e.g., 113 and,optionally, 119) and a trench isolation structure 110 that electricallyisolates these regions.

Specifically, the drain region 111 can be positioned within the firstintra-transistor well 104 at the top surface 120 of the substrate 101adjacent to the first side 131 of the gate structure 130 and the sourceregion 112 can be positioned within the fourth intra-transistor well 107at the top surface 120 of the substrate 101 adjacent to the second side132 of the gate structure 130. The drain region 111 and source region112 can be asymmetric with respect to the gate structure 130 and,specifically, the drain region 111 can be positioned farther from thegate structure 130 than the source region 112, as shown. The drainregion 111 and the source region 112 can each comprise doped regionshaving the first type conductivity at a relatively high conductivitylevel (e.g., a P+ drain region and a P+ source region).

Additionally, a contact region 113 (also referred to herein as a bodycontact region), having the second type conductivity at a relativelyhigh conductivity level (e.g., an N+ contact region), can be positionedwithin the fourth intra-transistor well 107 at the top surface 120 ofthe substrate 101 so as to allow that fourth intra-transistor well 107to be electrically biased. Within the fourth intra-transistor well, thesource region 112 can be positioned closer to the gate structure 130than the contact region 113. Optionally, as shown in FIG. 2, thetransistor 1B can further comprise a contact region 119, having thesecond type conductivity at a relatively high conductivity level (e.g.,an N+ contact region), within the second intra-transistor well 105 atthe top surface 120 of the substrate 101 so as to effectively form ajunction field effect transistor. Thus, the contact region 119 will becloser to the gate structure 130 than the drain region 111.

In any case, a patterned trench isolation structure 110 at the topsurface 120 of the substrate 101 can electrically isolate the drainregion 111, source region 112, and contact regions (e.g., the contactregion 113 and, if applicable, the contact region 119). This trenchisolation structure 110 can comprise, for example, a conventionalshallow trench isolation (STI) structure) comprising a patterned trench,which is filled with one or more isolation materials (e.g., silicondioxide (SiO₂), silicon nitride (SiN), silicon oxynitride (SiON), and/orany other suitable isolation material).

The transistor 1A, 1B can further comprise an intra-transistor band 103within the substrate 101. For purposes of this disclosure, an“intra-transistor band” refers to a band (i.e., a buried dopant implantregion within the substrate and separated from the top surface by somepredetermined distance), which is an active component of the transistor.The intra-transistor band 103 can be positioned in the substrate 101below and in contact with the first intra-transistor well 104, thesecond intra-transistor well 105, the third intra-transistor well 106and the fourth intra-transistor well 107. This intra-transistor band 103can have the first type conductivity (e.g., a P-band).

The semiconductor structure 100 can further comprise, within thesubstrate 101, a first isolation well 108, a second isolation well 109and an isolation band 102. For purposes of this disclosure, an“isolation well” refers to a well (i.e., a dopant implant region) thatelectrically isolates adjacent devices and/or components thereof. Suchisolation wells can be positioned at the top surface of thesemiconductor substrate and can extend vertically into the semiconductorsubstrate some predetermined depth (e.g., the same predetermined depth121 as the intra-transistor wells). For purposes of this disclosure, an“isolation band” refers to a band (i.e., a buried dopant implant regionwithin the substrate and separated from the top surface by somepredetermined distance), which electrically isolates devices andcomponents thereof from the lower portion of the substrate.

In this case, the first isolation well 108 can be positioned laterallyaround (i.e., can border) the transistor 1A, 1B (see the cross-sectiondiagram of FIG. 3) and can have the second type conductivity (e.g., anN-type isolation well). The second isolation well 109 can be positionedlaterally between the fourth intra-transistor well 107 and the firstisolation well 108, can have the first type conductivity (e.g., a P-typeisolation well), and can extend vertically to the intra-transistor band103. The isolation band 102 can be below and in contact with the firstisolation well 108 and the intra-transistor band 103. More specifically,the isolation band 102 can have vertical portion aligned below and incontact with the first isolation well 108. This vertical portion canfurther be positioned laterally around (i.e., can border) theintra-transistor band 103. Additionally, the isolation band 102 can havea horizontal portion that separates the bottom surface of theintra-transistor band 103 and the lower portion 191 of the substrate101. This isolation band 102 can have the second type conductivity(e.g., an N-band). The isolation band 102 in combination with the firstisolation well 108, which also has the second type conductivity, canelectrically isolate the transistor 1A, 1B from the lower portion 191 ofthe substrate 101 and from any adjacent devices (not shown) on thesubstrate 101.

It should be noted that, optionally, the semiconductor structure 100 canfurther comprise an additional contact region 115 that allows the well108 and, thereby the band 102 to be electrically biased. Morespecifically, the semiconductor structure 100 can further comprise acontact region 115, having the second type at a relatively highconductivity level (e.g., an N+ contact region), within the firstisolation well 108 at the top surface of the substrate 101 so as toallow that isolation well 108 and, thereby the band 102 below to beelectrically biased. As with the other contact regions 113, 119,described above, the contact region 115 can be electrically isolated bythe trench isolation region 110.

In such a semiconductor structure 100, the transistor 1A, 1B will have afully-depleted deep drain drift region 150 located within theintra-transistor band 103 between the second intra-transistor well 105and the isolation band 102. This fully-depleted drain drift region 150will ensure that the transistor 1A, 1B has a relatively high blockingvoltage. Furthermore, because the transistor 1A, 1B is electricallyisolated by the first isolation well 108 and isolation band 102 from thelower portion 191 of the substrate 101 and from adjacent devices on thesubstrate 101, the transistor 1A, 1B can be placed in relatively closeproximity to adjacent devices in order to increase device density on thesubstrate 101 with minimal risk of shorts.

Referring to FIG. 4, also disclosed herein is another semiconductorstructure 200 comprising a bulk semiconductor substrate 201. Forexample, the semiconductor substrate 201 can comprise a bulk siliconsubstrate or any other bulk semiconductor substrate. The semiconductorsubstrate 201 can have a first type conductivity (e.g., P-typeconductivity) at a relatively low conductivity level. For example, thesemiconductor substrate 201 can comprise a P− substrate.

The semiconductor structure 200 can further comprise a transistor 2 onthe semiconductor substrate 201 and, particularly, a P-type lateraldouble-diffused metal oxide semiconductor field effect transistor(PLDMOSFET) on the substrate 201.

Specifically, the transistor 2 can comprise a plurality ofintra-transistor wells 204 and 207 within the substrate 201. Forpurposes of this disclosure, an “intra-transistor well” refers to a well(i.e., a dopant implant region), which is an active component of thetransistor. These intra-transistor wells can comprise a firstintra-transistor well 204 having the first type conductivity (e.g., aP-well) and a second intra-transistor well 207 positioned laterallyadjacent to the first intra-transistor well 204 and having a second typeconductivity (e.g., an N-well). These intra-transistor wells 204 and 207can be positioned at the top surface 220 of the semiconductor substrate201 and can extend vertically into the semiconductor substrate 201 somepredetermined depth (e.g., a same predetermined depth 221).

It should be noted that the first intra-transistor well 204 can bephysically separated from the second intra-transistor well 207 by aspace 241, as shown. In this case, the space 241 between the firstintra-transistor well 204 and second intra-transistor well 207 will havethe same doping type and conductivity level as the lower portion 291 ofthe substrate 201 (e.g., P−). Alternatively, the first intra-transistorwell 204 can be immediately adjacent to (i.e., can abut) the secondintra-transistor well 207.

The transistor 2 can further comprise a gate structure 230 on the topsurface 220 of the substrate 201. A first side 231 of the gate structure230 can extend laterally over the first intra-transistor well 204. Asecond side 232 of the gate structure 230 can extend laterally over thesecond intra-transistor well 207 and can define the channel region 240of the transistor 2. The gate structure 230 can comprise a gatedielectric layer (e.g., a gate oxide layer, a high-k gate dielectriclayer or other suitable gate dielectric layer) and a gate conductorlayer (e.g., a polysilicon gate conductor layer, a metal gate conductorlayer, a dual work function gate conductor layer or other suitable gateconductor layer) on the gate dielectric layer.

The transistor 2 can further comprise, at the top surface 220 of thesubstrate 201 on either side of the gate structure 230, a drain region211, a source region 212, various contact regions (e.g., 213 and 219)and a trench isolation structure 210 that electrically isolates theseregions.

Specifically, the transistor 2 can further comprise a drain region 211within the first intra-transistor well 204 at the top surface 220 of thesubstrate 201 adjacent to the first side 231 of the gate structure 230and a source region 212 within the second intra-transistor well 207 atthe top surface 220 of the substrate 201 adjacent to the second side 232of the gate structure 230. The source region 212 and drain region 211can be asymmetric with respect to the gate structure 230 and,specifically, the drain region 211 can be positioned farther from thegate structure 230 than the source region 212, as shown. The drainregion 211 and the source region 212 can comprise doped regions havingthe first type conductivity at a relatively high conductivity level(e.g., a P+ drain region and a P+ source region).

The transistor 2 can further comprise an intra-transistor band 203within the substrate 201. For purposes of this disclosure, an“intra-transistor band” refers to a band (i.e., a buried dopant implantregion within the substrate and separated from the top surface by somepredetermined distance) that is an active component of the transistor.The intra-transistor band 203 can be in the substrate 201 below and incontact with the first intra-transistor well 204 and the secondintra-transistor well 207. This intra-transistor band 203 can have thefirst type conductivity (e.g., a P-band).

Additionally, a contact region 213 (also referred to herein as a bodycontact region), having the second type conductivity at a relativelyhigh conductivity level (e.g., an N+ contact region), can be positionedwithin the second intra-transistor well 207 at the top surface 220 ofthe substrate 201 so as to allow that second intra-transistor well 207to be electrically biased. Within the second intra-transistor well, thesource region 212 can be positioned closer to the gate structure 230than the contact region 213. The transistor 2 can further compriseanother contact region 219, having the second type conductivity at arelatively high conductivity level (e.g., an N+ contact region), withinthe first intra-transistor well 204 at the top surface 220 of thesubstrate 201 so as to effectively form a junction field effecttransistor. Within the first intra-transistor well 204, the contactregion 219 can be positioned closer to the gate structure 230 than thedrain region 211.

In any case, a patterned trench isolation structure 210 at the topsurface 220 of the substrate 201 can electrically isolate the drainregion 211, source region 212, and contact regions 213, 219. This trenchisolation structure 210 can comprise, for example, a conventionalshallow trench isolation (STI) structure) comprising a patterned trench,which is filled with one or more isolation materials (e.g., silicondioxide (SiO₂), silicon nitride (SiN), silicon oxynitride (SiON), and/orany other suitable isolation material).

The semiconductor structure 200 can further comprise, within thesubstrate 201, a first isolation well 208, a second isolation well 209and an isolation band 202. For purposes of this disclosure, an“isolation well refers” to a well (i.e., a dopant implant region) thatelectrically isolates adjacent devices and/or components thereof. Suchisolation wells can be positioned at the top surface of thesemiconductor substrate and can extend vertically into the semiconductorsubstrate some predetermined depth (e.g., the same predetermined depth221 as the intra-transistor wells). For purposes of this disclosure, an“isolation band” refers to a band (i.e., a buried dopant implant regionwithin the substrate and separated from the top surface by somepredetermined distance), which electrically isolates devices andcomponents thereof from the lower portion of the substrate.

In this case, the first isolation well 208 can be positioned laterallyaround (i.e., can border) the transistor 2 (see the cross-sectiondiagram of FIG. 5) and can have the second type conductivity (e.g., anN-type isolation well). The second isolation well 209 can be positionedlaterally between the second intra-transistor well 207 and the firstisolation well 208, can have the first type conductivity (e.g., a P-typeisolation well) and can extend vertically to the intra-transistor band203. The isolation band 202 can be below and in contact with the firstisolation well 208 and the intra-transistor band 203. More specifically,the isolation band 202 can have vertical portion aligned below and incontact with the first isolation well 208. This vertical portion canfurther be positioned laterally around (i.e., can border) theintra-transistor band 203. Additionally, the isolation band 202 can havea horizontal portion that separates the bottom surface of theintra-transistor band 203 and the lower portion 291 of the substrate201. This isolation band 202 can have the second type conductivity(e.g., an N-band). The isolation band 202 in combination with the firstisolation well 208, which also has the second type conductivity, canelectrically isolate the transistor 2 from the lower portion 291 of thesubstrate 201 and from any adjacent devices (not shown) on the substrate201.

It should be noted that, optionally, the semiconductor structure 200 canfurther comprise an additional contact region 215 that allows the well208 and, thereby the band 202 to be electrically biased. Morespecifically, the semiconductor structure 200 can further comprise acontact region 215, having the second conductivity type at a relativelyhigh conductivity level (e.g., an N+ contact region), within the firstisolation well 208 at the top surface 220 of the substrate 201 so as toallow that isolation well 208 and, thereby the band 202 below to beelectrically biased. As with the other contact regions 213, 219,described above, the contact region 215 can be electrically isolated bythe trench isolation region 210.

In such a semiconductor structure 200, the transistor 2 will have afully-depleted deep drain drift region 250 located within theintra-transistor band 203 and first intra-transistor well 204 betweencontact region 219 and the isolation band 202. This fully-depleted draindrift region 250 will ensure that the transistor 2 has a relatively highblocking voltage. Furthermore, because the transistor 2 is electricallyisolated by the first isolation well 208 and isolation band 202 from thelower portion 291 of the substrate 201 and from adjacent devices on thesubstrate 201, the transistor 2 can be placed in relatively closeproximity to adjacent devices in order to increase device density on thesubstrate 201 with minimal risk of shorts.

Referring to FIGS. 6 and 7 disclosed herein is yet another semiconductorstructure 600 comprising a bulk semiconductor substrate 601. Forexample, the semiconductor substrate 601 can comprise a bulk siliconsubstrate or any other bulk semiconductor substrate. The semiconductorsubstrate 601 can have a first type conductivity (e.g., P-typeconductivity) at a relatively low conductivity level. For example, thesemiconductor substrate 601 can comprise a P− substrate.

The semiconductor structure 600 can further comprise a transistor 6A, asin FIG. 6, or 6B, as in FIG. 7, on the semiconductor substrate 601 and,particularly, an N-type lateral double-diffused metal oxidesemiconductor field effect transistor (NLDMOSFET) on the substrate 601.

Specifically, this transistor 6A, 6B can comprise plurality ofintra-transistor wells within the substrate 601. For purposes of thisdisclosure, an “intra-transistor well” refers to a well (i.e., a dopantimplant region), which is an active component of the transistor. Theseintra-transistor wells can comprise a first intra-transistor well 604having a second type conductivity (e.g., an N-well); a secondintra-transistor well 605 within the first intra-transistor well 604 andhaving the first type conductivity (e.g., a P-well); and a thirdintra-transistor well 607 positioned laterally adjacent to the firstintra-transistor well 604 and having the first type conductivity (e.g.,another P-well). In this case, the first intra-transistor well 604 andthe third intra-transistor well 607 can extend a first depth 621 intothe substrate 601 from the top surface 620, the second intra-transistorwell 605 can extend a second depth 622 into the substrate 601 from thetop surface 620 and the first depth 621 can be deeper than the seconddepth 622 (i.e., the second intra-transistor 605 well can be a moreshallow well than the first and third intra-transistor wells).

It should be noted that the first intra-transistor well 604 can bephysically separated from the third intra-transistor well 607 by a space641, as shown. In this case, the space 641 between the firstintra-transistor well 604 and third intra-transistor well 607 will havethe same doping type and conductivity level as the lower portion 691 ofthe substrate 601 (e.g., P−). Alternatively, the first intra-transistorwell 604 can be immediately adjacent to (i.e., can abut) the thirdintra-transistor well 607 (not shown).

The transistor 6 can further comprise a gate structure 630 on the topsurface 620 of the substrate 601. A first side 631 of the gate structure630 can extend laterally over the first intra-transistor well 604. Asecond side 632 of the gate structure 630 can extend laterally over thethird intra-transistor well 607 and can define the channel region 640 ofthe transistor 6. The gate structure 630 can comprise a gate dielectriclayer (e.g., a gate oxide layer, a high-k gate dielectric layer or othersuitable gate dielectric layer) and a gate conductor layer (e.g., apolysilicon gate conductor layer, a metal gate conductor layer, a dualwork function gate conductor layer or other suitable gate conductorlayer) on the gate dielectric layer.

The transistor 6 can further comprise, at the top surface 620 of thesubstrate 601 on either side of the gate structure 630, a drain region611, a source region 612, various contact regions (e.g., 613 and,optionally, 619) and a trench isolation structure 610 that electricallyisolates these regions.

Specifically, the transistor can comprise a drain region 611 within thefirst intra-transistor within the first intra-transistor well 604 at thetop surface 620 of the substrate 601 adjacent to the first side 631 ofthe gate structure 630 and a source region 612 within the thirdintra-transistor well 607 at the top surface 620 of the substrate 601adjacent to the second side 632 of the gate structure 630. The drainregion 611 and source region 612 can be asymmetric with respect to thegate structure 630 and, specifically, the drain region 611 can bepositioned farther from the gate structure 630 than the source region612, as shown. The drain region 611 and the source region 612 can eachhave the second type conductivity at a relatively high conductivitylevel (e.g., a N+ drain region and a N+ source region).

Additionally, a contact region 613 (also referred to herein as a bodycontact region), having the first conductivity type at a relatively highconductivity level (e.g., a P+ contact region), can be positioned withinthe third intra-transistor well 607 at the top surface 620 of thesubstrate 601 so as to allow that third intra-transistor well 607 to beelectrically biased. Within the third intra-transistor well 607, thesource region 612 can be positioned closer to the gate structure 630than the contact region 613. Optionally, as shown in FIG. 7, thetransistor 6B can further comprise a contact region 619, having thefirst conductivity type at a relatively high conductivity level (e.g.,another P+ contact region), within the second intra-transistor well 605at the top surface 620 of the substrate 601 so as to effectively form ajunction field effect transistor. Within the first intra-transistor well604, the contact region 619 can be positioned closer to the gatestructure 630 than the drain region 611.

In any case, a patterned trench isolation structure 610 at the topsurface 620 of the substrate 601 can electrically isolate the drainregion 611, source region 612, and contact regions (e.g., the contactregion 613 and, if applicable, the contact region 619). This trenchisolation structure 610 can comprise, for example, a conventionalshallow trench isolation (STI) structure) comprising a patterned trench,which is filled with one or more isolation materials (e.g., silicondioxide (SiO₂), silicon nitride (SiN), silicon oxynitride (SiON), and/orany other suitable isolation material).

The semiconductor structure 600 can further comprise, within thesubstrate 601, a first isolation band 603, a first isolation well 608, asecond isolation well 609 and a second isolation band 602. For purposesof this disclosure, an “isolation well” refers to a well (i.e., a dopantimplant region) that electrically isolates adjacent devices and/orcomponents thereof. Such isolation wells can be positioned at the topsurface of the semiconductor substrate and can extend vertically intothe semiconductor substrate some predetermined depth (e.g., the samepredetermined depth 621 as the first and third intra-transistor wells).For purposes of this disclosure, an “isolation band” refers to a band(i.e., a buried dopant implant region within the substrate and separatedfrom the top surface by some predetermined distance), which electricallyisolates devices and components thereof from the lower portion of thesubstrate.

In this case, the first isolation band 603 can be positioned below andin contact with the first intra-transistor well 604. This firstisolation band 603 can have the first type conductivity (e.g., a P-typeisolation band). The first isolation well 608 can have the second typeconductivity (e.g., an N-type isolation well) and can be positionedlaterally around (i.e., can border) the transistor 6A, 6B (see thecross-section diagram of FIG. 8). The second isolation well 609 can havethe first type conductivity (e.g., a P-type isolation well) and can bepositioned laterally between the first isolation well 608 and the firstintra-transistor well 604 of the transistor 6A, 6B and can extendvertically to the first isolation band 603. The second isolation band602 can be below and in contact with the first isolation well 608, thefirst isolation band 603 and the third intra-transistor well 607 of thetransistor 6A, 6B. More specifically, the second isolation band 602 canhave a vertical portion aligned below and in contact with the firstisolation well 608. Additionally, the second isolation band 602 can havea horizontal portion that separates the bottom surfaces of the firstisolation band 603 and the third intra-transistor well 607 from thelower portion 691 of the substrate 601. The second isolation band 602can have the second type conductivity (e.g., an N-type isolation band).The second isolation band 602 in combination with the first isolationwell 608, which also has the second type conductivity, can electricallyisolate the transistor 6A, 6B from the lower portion 691 of thesubstrate 601 and from any adjacent devices (not shown) on the substrate601.

It should be noted that, optionally, the semiconductor structure 600 canfurther comprise additional contact regions 614 and 615 that allow thewells 609 and 608 and, thereby the bands 603 and 602, respectively, tobe electrically biased. More specifically, the semiconductor structure600 can further comprise a contact region 614, having the firstconductivity type at a relatively high conductivity level (e.g., a P+contact region), within the second isolation well 609 at the top surface620 of the substrate 601 so as to allow that isolation well 609 and,thereby the band 603 below to be electrically biased. The semiconductorstructure 600 can also further comprise a contact region 615, having thesecond conductivity type at a relatively high conductivity level (e.g.,an N+ contact region), within the first isolation well 608 at the topsurface 620 of the substrate 601 so as to allow that isolation well 608and, thereby the band 602 below to be electrically biased. As with theother contact regions 613, 619, described above, the contact regions 614and 615 can be electrically isolated by the trench isolation region 610.

In such a semiconductor structure 600, the transistor 6A, 6B will have afully-depleted deep drain drift region 650 located within the firstintra-transistor well 604 between the second intra-transistor well 605and the first isolation band 603. This fully-depleted drain drift region650 will ensure that the transistor 6A, 6B has a relatively highblocking voltage. Furthermore, because the transistor 6A, 6B iselectrically isolated by the first isolation well 608 and isolation band602 from the lower portion 691 of the substrate 601 and from adjacentdevices on the substrate 601, the transistor 6A, 6B can be placed inrelatively close proximity to adjacent devices in order to increasedevice density on the substrate 601 with minimal risk of shorts.

Referring to FIG. 9 disclosed herein is yet another semiconductorstructure 900 comprising a bulk semiconductor substrate 901. Forexample, the semiconductor substrate 901 can comprise a bulk siliconsubstrate or any other bulk semiconductor substrate. The semiconductorsubstrate 901 can have a first type conductivity (e.g., P-typeconductivity) at a relatively low conductivity level. For example, thesemiconductor substrate 901 can comprise a P− substrate.

The semiconductor structure 900 can further comprise a transistor 9 onthe semiconductor substrate 901 and, particularly, an N-type lateraldouble-diffused metal oxide semiconductor field effect transistor(NLDMOSFET) on the substrate 901.

Specifically, this transistor 9 can comprise plurality ofintra-transistor wells within the substrate 901. For purposes of thisdisclosure, an “intra-transistor well” refers to a well (i.e., a dopantimplant region), which is an active component of the transistor. Theseintra-transistor wells can comprise a first intra-transistor well 904having a second type conductivity (e.g., an N-well) and a secondintra-transistor well 907 positioned laterally adjacent to the firstintra-transistor well 904 and having the first type conductivity (e.g.,a P-well). Each of these intra-transistor wells 904 and 907 can bepositioned at the top surface 920 of the semiconductor substrate 901 andcan extend vertically into the semiconductor substrate 901 somepredetermined depth (e.g., a same predetermined depth 921).

It should be noted that the first intra-transistor well 904 can bephysically separated from the second intra-transistor well 907 by aspace 941, as shown. In this case, the space 941 between the firstintra-transistor well 904 and second intra-transistor well 907 will havethe same doping type and conductivity level as the lower portion 991 ofthe substrate 901 (e.g., P−). Alternatively, the first intra-transistorwell 904 can be immediately adjacent to (i.e., can abut) the secondintra-transistor well 907 (not shown).

The transistor 9 can further comprise a gate structure 930 on the topsurface 920 of the substrate 901. A first side 931 of the gate structure930 can extend laterally over the first intra-transistor well 904. Asecond side 932 of the gate structure 930 can extend laterally over thesecond intra-transistor well 907 and can define the channel region 940of the transistor 9. The gate structure 930 can comprise a gatedielectric layer (e.g., a gate oxide layer, a high-k gate dielectriclayer or other suitable gate dielectric layer) and a gate conductorlayer (e.g., a polysilicon gate conductor layer, a metal gate conductorlayer, a dual work function gate conductor layer or other suitable gateconductor layer) on the gate dielectric layer.

The transistor 9 can further comprise, at the top surface 920 of thesubstrate 901 on either side of the gate structure 930, a drain region911, a source region 612, various contact regions (e.g., 913 and 919)and a trench isolation structure 910 that electrically isolates theseregions.

Specifically, the transistor 9 can comprise a drain region 911 withinthe first intra-transistor within the first intra-transistor well 904 atthe top surface 920 of the substrate 901 adjacent to the first side 931of the gate structure 930 and a source region 912 within the secondintra-transistor well 907 at the top surface 920 of the substrate 901adjacent to the second side 932 of the gate structure 930. The drainregion 911 and source region 912 can be asymmetric with respect to thegate structure 930 and, specifically, the drain region 911 can bepositioned farther from the gate structure 930 than the source region912, as shown. The drain region 911 and the source region 912 can eachhave the second type conductivity at a relatively high conductivitylevel (e.g., a N+ drain region and a N+ source region).

Additionally, a contact region 913 (also referred to herein as a bodycontact region), having the first conductivity type at a relatively highconductivity level (e.g., a P+ contact region), can be positioned withinthe second intra-transistor well 907 at the top surface 920 of thesubstrate 901 so as to allow that second intra-transistor well 907 to beelectrically biased. Within the second intra-transistor well, the sourceregion 912 can be positioned closer to the gate structure 930 than thecontact region 913. The transistor 9 can further comprise a contactregion 919, having the first conductivity type at a relatively highconductivity level (e.g., another P+ contact region), within the firstintra-transistor well 905 at the top surface 920 of the substrate 901 soas to effectively form a junction field effect transistor. Within thefirst intra-transistor well 904, the contact region 919 can bepositioned closer to the gate structure 930 than the drain region 911.

In any case, a patterned trench isolation structure 910 at the topsurface 920 of the substrate 901 can electrically isolate the drainregion 911, source region 912, and contact regions 913, 919. This trenchisolation structure 910 can comprise, for example, a conventionalshallow trench isolation (STI) structure) comprising a patterned trench,which is filled with one or more isolation materials (e.g., silicondioxide (SiO₂), silicon nitride (SiN), silicon oxynitride (SiON), and/orany other suitable isolation material).

The semiconductor structure 900 can further comprise, within thesubstrate 901, a first isolation band 903, a first isolation well 908, asecond isolation well 909 and a second isolation band 902. For purposesof this disclosure, an “isolation well” refers to a well (i.e., a dopantimplant region) that electrically isolates adjacent devices and/orcomponents thereof. Such isolation wells can be positioned at the topsurface of the semiconductor substrate and can extend vertically intothe semiconductor substrate some predetermined depth (e.g., the samepredetermined depth 921 as the first and second intra-transistor wells).For purposes of this disclosure, an “isolation band” refers to a band(i.e., a buried dopant implant region within the substrate and separatedfrom the top surface by some predetermined distance), which electricallyisolates devices and components thereof from the lower portion of thesubstrate.

In this case, the first isolation band 903 can be positioned below andin contact with the first intra-transistor well 904. This firstisolation band 903 can have the first type conductivity (e.g., a P-typeisolation band). The first isolation well 908 can have the second typeconductivity (e.g., an N-type isolation well) and can be positionedlaterally around (i.e., can border) the transistor 9 (see thecross-section diagram of FIG. 10). The second isolation well 909 canhave the first type conductivity (e.g., a P-type isolation well) and canbe positioned laterally between the first isolation well 908 and thefirst intra-transistor well 904 of the transistor 9 and can extendvertically to the first isolation band 903. The second isolation band902 can be below and in contact with the first isolation well 908, thefirst isolation band 903 and the second intra-transistor well 907 of thetransistor 9. More specifically, the second isolation band 902 can havea vertical portion aligned below and in contact with the first isolationwell 608. Additionally, the second isolation band 902 can have ahorizontal portion that separates the bottom surfaces of the firstisolation band 903 and the second intra-transistor well 907 from thelower portion 991 of the substrate 901. The second isolation band 902can have the second type conductivity (e.g., an N-type isolation band).The second isolation band 902 in combination with the first isolationwell 908, which also has the second type conductivity, can electricallyisolate the transistor 9 from the lower portion 991 of the substrate 901and from any adjacent devices (not shown) on the substrate 901.

It should be noted that, optionally, the semiconductor structure 900 canfurther comprise additional contact regions 914 and 915 that allow thewells 909 and 908 and, thereby the bands 903 and 902, respectively, tobe electrically biased. More specifically, the semiconductor structure900 can further comprise a contact region 914, having the firstconductivity type at a relatively high conductivity level (e.g., a P+contact region), within the second isolation well 909 at the top surface920 of the substrate 901 so as to allow that isolation well 909 and,thereby the band 903 below to be electrically biased. The semiconductorstructure 900 can also further comprise a contact region 915, having thesecond conductivity type at a relatively high conductivity level (e.g.,an N+ contact region), within the first isolation well 908 at the topsurface 920 of the substrate 901 so as to allow that isolation well 908and, thereby the band 902 below to be electrically biased. As with theother contact regions 913, 919, described above, the contact regions 914and 915 can be electrically isolated by the trench isolation region 910.

In such a semiconductor structure 900, the transistor 9 will have afully depleted deep drain drift region 950 located within the firstintra-transistor well 904 between contact region 919 and the firstisolation band 903. This fully-depleted drain drift region 950 willensure that the transistor 9 has a relatively high blocking voltage.Furthermore, because the transistor 9 is electrically isolated by thefirst isolation well 908 and isolation band 902 from the lower portion991 of the substrate 901 and from adjacent devices on the substrate 901,the transistor 9 can be placed in relatively close proximity to adjacentdevices in order to increase device density on the substrate 901 withminimal risk of shorts.

Also disclosed herein are semiconductor structures comprising multipleones of the above-described transistors in either logic circuit (e.g.,inverter) configuration or a stacked LDMOSFET configuration.

For example, FIG. 11 is a cross-section diagram illustrating asemiconductor structure 1100 wherein the transistor 1A of FIGS. 1 and 6Aof FIG. 6 are arranged on the same substrate 1101 as a logic circuit(e.g., inverter) configuration. That is, the transistor 1A (e.g., aPLDMOSFET) is positioned laterally adjacent to the transistor 6A (e.g.,an NLDMOSFET) on the same substrate 1101. It should be noted that inthis case the transistors 1A and 6A can be laterally surrounded byisolation wells 108 and 608, respectively, having the second typeconductivity, as discussed in detail above. However, the portion ofthese wells 108, 608 between the transistors 1A and 6A can be shared.Similarly, each transistor 1A and 6A can be electrically isolated fromthe lower portion 1191 of the semiconductor substrate 1101 below byisolation bands 102 and 602, respectively, having the second typeconductivity, as discussed in detail above. However, these isolationbands 102, 602 can be continuous (i.e., can form adjacent portions ofthe same band that extends laterally under both transistors).

Similarly, FIG. 12 is a cross-section diagram illustrating asemiconductor structure 1200 wherein the transistor 1B of FIGS. 2 and 6Bof FIG. 7 are arranged on the same substrate 1201 as a logic circuit(e.g., inverter) configuration. That is, the transistor 1B (e.g., aPLDMOSFET) is positioned laterally adjacent to the transistor 6B (e.g.,an NLDMOSFET) on the same substrate 1201. It should be noted that inthis case the transistors 1B and 6B can be laterally surrounded byisolation wells 108 and 608, respectively, having the second typeconductivity, as discussed in detail above. However, the portion ofthese wells 108, 608 between the transistors 1B and 6B can be shared.Similarly, each transistor 1B and 6B can be electrically isolated fromthe lower portion 1291 of the semiconductor substrate 1201 below byisolation bands 102 and 602, respectively, having the second typeconductivity, as discussed in detail above. However, these isolationbands 102, 602 can be continuous (i.e., can form adjacent portions ofthe same band that extends laterally under both transistors).

Similarly, FIG. 13 is a cross-section diagram illustrating asemiconductor structure 1300 wherein the transistor 2 of FIGS. 4 and 9of FIG. 9 are arranged on the same substrate 1301 as a logic circuit(e.g., inverter) configuration. That is, the transistor 2 (e.g., aPLDMOSFET) is positioned laterally adjacent to the transistor 9 (e.g.,an NLDMOSFET) on the same substrate 1301. It should be noted that inthis case the transistors 2 and 9 can be laterally surrounded byisolation wells 208 and 908, respectively, having the second typeconductivity, as discussed in detail above. However, the portion ofthese wells 208, 908 between the transistors 2 and 9 can be shared.Similarly, each transistor 2 and 9 can be electrically isolated from thelower portion 1391 of the semiconductor substrate 1301 below byisolation bands 202 and 902, respectively, having the second typeconductivity, as discussed in detail above. However, these isolationbands 202, 902 can be continuous (i.e., can form adjacent portions ofthe same band that extends laterally under both transistors).

FIG. 14 is a cross-section diagram illustrating a semiconductorstructure 1400 wherein two of transistors 1A of FIG. 1 (e.g., twoPDLMOSFETs) are stacked together on the same substrate 1401. That is, afirst transistor 1A is positioned laterally adjacent to anothertransistor 1A on the same substrate 1401. It should be noted that inthis case two the transistors 1A can share a fourth intra-transistorwell 107 (within which their respective source regions 112 are located)as well as the contact region 113 to that well 107. The two transistors1A can be laterally surrounded by a single isolation well 108, havingthe second type conductivity, as discussed in detail above.Additionally, the two transistors 1A can be electrically isolated fromthe lower portion 1491 of the semiconductor substrate 1401 below by asingle isolation band 102 that extends laterally below both transistors.It should be understood that the other disclosed LDMOSFETs 1B, 2, 6A, 6Band 9 can be stacked together in a similar manner.

Those skilled in the art will recognize that the above-describedsemiconductor structures can be formed using standard complementarymetal oxide semiconductor (CMOS) fabrication processes. For example,multiple masked dopant implantation processes can be performed tocreate, within a bulk semiconductor substrate, the multiple discretedopant implant regions (i.e., the various wells and bands described)having the desired conductivity type and level and as well as therelative positioning. Additional masked dopant implantation processescan be performed in order to form the source, drain and contact regionsdescribed. Alternatively, multiple in-situ doped epitaxial growthprocesses can be performed in order to form the source, drain andcontact regions described.

Therefore, disclosed above are semiconductor structures. Eachsemiconductor structure can comprise a substrate and a laterallydouble-diffused metal oxide semiconductor field effect transistor(LDMOSFET) on the substrate. Each LDMOSFET can have a fully-depleteddeep drain drift region (i.e., a fully depleted deep ballast resistorregion) for providing a relatively high blocking voltage. Differentconfigurations for the drain drift regions are disclosed and thesedifferent configurations can also vary as a function of the conductivitytype of the LDMOSFET. Additionally, each semiconductor structure cancomprise an isolation band positioned below the LDMOSFET and anisolation well positioned laterally around the LDMOSFET and extendingvertically to the isolation band such that the LDMOSFET is electricallyisolated from both a lower portion of the substrate and any adjacentdevices on the substrate.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of this disclosure.As used herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

The descriptions of the various embodiments of the present inventionhave been presented above for purposes of illustration, but are notintended to be exhaustive or limited to the embodiments disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiments, the practical application or technicalimprovement over technologies found in the marketplace, or to enableothers of ordinary skill in the art to understand the embodimentsdisclosed herein.

What is claimed is:
 1. A semiconductor structure comprising: asemiconductor substrate having a top surface and a first typeconductivity; a transistor on said semiconductor substrate, saidtransistor comprising: a first intra-transistor well in saidsemiconductor substrate and having a second type conductivity; a secondintra-transistor well in said semiconductor substrate within said firstintra-transistor well and having said first type conductivity, saidfirst intra-transistor well extending deeper into said semiconductorsubstrate than said second intra-transistor well; a thirdintra-transistor well in said semiconductor substrate, positionedlaterally adjacent to said first intra-transistor well and having saidfirst type conductivity, said first intra-transistor well and said thirdintra-transistor well extending a same depth into said semiconductorsubstrate; a drain region within said first intra-transistor well atsaid top surface of said semiconductor substrate; and, a source regionwithin said third intra-transistor well at said top surface of saidsemiconductor substrate, said drain region and said source region havingsaid second type conductivity; a first isolation band in saidsemiconductor substrate below and in contact with said firstintra-transistor well, said first isolation band having said first typeconductivity; a first isolation well positioned laterally around saidtransistor and having said second type conductivity; a second isolationwell positioned laterally between said first intra-transistor well andsaid first isolation well and extending vertically to said firstisolation band, said second isolation well having said first typeconductivity; and a second isolation band in said semiconductorsubstrate and having said second type conductivity, said secondisolation band being below said first isolation well, said firstisolation band and said second intra-transistor well such that saidtransistor is electrically isolated from a lower portion of saidsemiconductor substrate, said first intra-transistor well having a draindrift region between said second intra-transistor well and said firstisolation band.
 2. The semiconductor structure of claim 1, said draindrift region being fully depleted.
 3. The semiconductor structure ofclaim 1, further comprising a gate structure on said top surface closerto said source region than said drain region, said gate structure havinga first side above said first intra-transistor well and a second sideabove said third intra-transistor well.
 4. The semiconductor structureof claim 1, said third intra-transistor well being immediately adjacentto said first intra-transistor well.
 5. The semiconductor structure ofclaim 1, said third intra-transistor well being physically separatedfrom said first intra-transistor well.
 6. The semiconductor structure ofclaim 1, further comprising a contact region within said secondintra-transistor well at said top surface of said semiconductorsubstrate, said contact region having said first type conductivity. 7.The semiconductor structure of claim 1, said transistor comprising aN-type transistor and said semiconductor structure further comprising aP-type transistor on said semiconductor substrate positioned laterallyadjacent to said first isolation well, said second isolation bandextending laterally below said P-type transistor.
 8. A semiconductorstructure comprising: a semiconductor substrate having a top surface anda first type conductivity; a transistor on said semiconductor substrate,said transistor comprising: a first intra-transistor well in saidsemiconductor substrate and having a second type conductivity; a secondintra-transistor well in said semiconductor substrate within said firstintra-transistor well and having said first type conductivity, saidfirst intra-transistor well extending deeper into said semiconductorsubstrate than said second intra-transistor well; a thirdintra-transistor well in said semiconductor substrate, positionedlaterally adjacent to said first intra-transistor well and having saidfirst type conductivity, said first intra-transistor well and said thirdintra-transistor well being physically separated and extending a samedepth into said semiconductor substrate; a drain region within saidfirst intra-transistor well at said top surface of said semiconductorsubstrate; and, a source region within said third intra-transistor wellat said top surface of said semiconductor substrate, said drain regionand said source region having said second type conductivity; a firstisolation band in said semiconductor substrate below and in contact withsaid first intra-transistor well, said first isolation band having saidfirst type conductivity; a first isolation well positioned laterallyaround said transistor and having said second type conductivity; asecond isolation well positioned laterally between said firstintra-transistor well and said first isolation well and extendingvertically to said first isolation band, said second isolation wellhaving said first type conductivity; and a second isolation band in saidsemiconductor substrate and having said second type conductivity, saidsecond isolation band being below said first isolation well, said firstisolation band and said second intra-transistor well such that saidtransistor is electrically isolated from a lower portion of saidsemiconductor substrate, said first intra-transistor well having a draindrift region between said second intra-transistor well and said firstisolation band.
 9. The semiconductor structure of claim 8, said draindrift region being fully depleted.
 10. The semiconductor structure ofclaim 8, further comprising a gate structure on said top surface closerto said source region than said drain region, said gate structure havinga first side above said first intra-transistor well and a second sideabove said third intra-transistor well.
 11. The semiconductor structureof claim 10, said gate structure being aligned above a space betweensaid first intra-transistor well and said third intra-transistor well,said space having a same conductivity type and level as a lower portionof said semiconductor substrate below said second isolation band. 12.The semiconductor structure of claim 8, further comprising a contactregion within said second intra-transistor well at said top surface ofsaid semiconductor substrate, said contact region having said first typeconductivity.
 13. The semiconductor structure of claim 8, saidtransistor comprising a N-type transistor and said semiconductorstructure further comprising a P-type transistor on said semiconductorsubstrate positioned laterally adjacent to said first isolation well,said second isolation band extending laterally below said P-typetransistor.
 14. A semiconductor structure comprising: a semiconductorsubstrate having a top surface and a first type conductivity; atransistor on said semiconductor substrate, said transistor comprising:a first intra-transistor well in said semiconductor substrate and havinga second type conductivity; a second intra-transistor well in saidsemiconductor substrate, positioned laterally adjacent to said firstintra-transistor well and having said first type conductivity, saidfirst intra-transistor well and said second intra-transistor wellextending a same depth into said semiconductor substrate; a drain regionwithin said first intra-transistor well at said top surface of saidsemiconductor substrate; a source region within said secondintra-transistor well at said top surface of said semiconductorsubstrate, said drain region and said source region having said secondtype conductivity; and, a contact region within said firstintra-transistor well at said top surface of said semiconductorsubstrate between said drain region and said second intra-transistorwell, said contact region having said first type conductivity; a firstisolation band in said semiconductor substrate below and in contact withsaid first intra-transistor well, said first isolation band having saidfirst type conductivity; a first isolation well positioned laterallyaround said transistor and having said second type conductivity; asecond isolation well positioned laterally between said firstintra-transistor well and said first isolation well and extendingvertically to said first isolation band, said second isolation wellhaving said first type conductivity; and a second isolation band in saidsemiconductor substrate and having said second type conductivity, saidsecond isolation band being below said first isolation well, said firstisolation band and said second intra-transistor well such that saidtransistor is electrically isolated from a lower portion of saidsemiconductor substrate, said first intra-transistor well having a draindrift region between said contact region and said first isolation band.15. The semiconductor structure of claim 14, said drain drift regionbeing fully depleted.
 16. The semiconductor structure of claim 14,further comprising a gate structure on said top surface closer to saidsource region than said drain region, said gate structure having a firstside above said first intra-transistor well and a second side above saidsecond intra-transistor well.
 17. The semiconductor structure of claim14, said first intra-transistor well being immediately adjacent to saidsecond intra-transistor well.
 18. The semiconductor structure of claim14, said first intra-transistor well being physically separated fromsaid second intra-transistor well.
 19. The semiconductor structure ofclaim 18, further comprising a gate structure aligned above a spacebetween said first intra-transistor and said second intra-transistorwell, said space having a same conductivity type and level as a lowerportion of said semiconductor substrate below said second isolationband.
 20. The semiconductor structure of claim 14, said transistorcomprising an N-type transistor and said semiconductor structure furthercomprising a P-type transistor on said semiconductor substratepositioned laterally adjacent to said first isolation well, said secondisolation band extending laterally below said P-type transistor.